24进制计数器 - 我的第一个FPGA程序
新到手了一片FPGA，花了两天时间，看了一些书，算是懂了VHDL最基础的一点点。总算是把这份24进制计数器做出来了。现在我分以下几个部分总结：
程序代码对于软件操作的总结对于VHDL语言的总结
程序代码
library IEEE;
use IEEE.STD_LOGIC_1164.
ALL;
use IEEE.STD_LOGIC_unsigned.
ALL;
entity Module01
is
Port ( cp :
in STD_LOGIC;
rst :
in STD_LOGIC;
Wela :
out STD_LOGIC_VECTOR (
7 downto 0);
Dula :
out STD_LOGIC_VECTOR (
5 downto 0));
end Module01;
architecture Behavioral
of Module01
is
signal i :
integer range 0 to 15;
signal Count :
integer range 0 to 65535;
signal Timer0Value :
integer range 0 to 65535;
signal Timer0IntSt :
STD_LOGIC;
TYPE BCD
IS ARRAY (
NATURAL RANGE <>)
OF
STD_LOGIC_VECTOR(
3 DOWNTO 0);
SIGNAL DATA : BCD (
1 DOWNTO 0);
TYPE SMG_Buff_Type
IS ARRAY (
NATURAL RANGE <>)
OF
STD_LOGIC_VECTOR(
7 DOWNTO 0);
SIGNAL SMG_Buff : SMG_Buff_Type (
5 DOWNTO 0) := (X
"ff",X
"ff",X
"ff",X
"ff",X
"ff",X
"ff");
CONSTANT SMG_Code : SMG_Buff_Type (
0 to 9) :=
(X
"c0", X
"f9", X
"a4", X
"b0", X
"99", X
"92", X
"82", X
"f8", X
"80", X
"90");
begin
process(cp)
begin
if cp=
'1' and cp
'event then
if rst=
'0' then
Timer0Value <=
0;
Timer0IntSt <=
'0';
else
if Timer0Value =
24999 then
Timer0Value <=
0;
Timer0IntSt <=
not Timer0IntSt;
else
Timer0Value <= Timer0Value +
1;
end if;
end if;
end if;
end process;
process(Timer0IntSt)
begin
if rst=
'0' then
Count <=
0;
DATA <= (X
"0", X
"0");
SMG_Buff <= (X
"ff",X
"ff",X
"ff",X
"ff",X
"ff",X
"ff");
else
if Timer0IntSt=
'1' and Timer0IntSt
'event then
if Count=
999 then
Count <=
0;
if DATA(
0)=
"1001" then
DATA(
0) <=
"0000";
DATA(
1) <= DATA(
1) +
1;
elsif DATA(
0)=
"0011" and DATA(
1)=
"0010" then
DATA(
0) <=
"0000";
DATA(
1) <=
"0000";
else
DATA(
0) <= DATA(
0) +
1;
end if;
SMG_Buff(
0) <= SMG_Code(CONV_INTEGER(DATA(
0)));
SMG_Buff(
1) <= SMG_Code(CONV_INTEGER(DATA(
1)));
else
Count <= Count +
1;
end if;
Dula <=
"111111";
Wela <= SMG_Buff(i);
Dula <=
"111111" - (
2**i);
if i=
5 then
i <=
0;
else
i <= i+
1;
end if;
end if;
end if;
end process;
end Behavioral;
对于软件操作的总结
Save 每次进行软件操作前要先保存。 Check Syntax 每次拿不准的时候，可以通过这一项进行语法检测。 Generate Programming File 这一项可以完成所有的检测项，但要注意进程中间是否有占用CPU的进程，一般这一项计算速度并不算慢，拖慢速度的一般是有其他进程占用CPU。特别提醒：打开了iMPACT就不要关闭了，这玩意儿经常关不掉，会有几个占用CPU的进程遗留。
对于VHDL语言的总结
指定BCD为4位的一个数组类型，然后data以BCD为数组类型有两个元素。
TYPE BCD
IS ARRAY (
NATURAL RANGE <>)
OF
STD_LOGIC_VECTOR(
3 DOWNTO 0);
SIGNAL DATA : BCD (
1 DOWNTO 0);
变量初始化赋值用:=
TYPE SMG_Buff_Type
IS ARRAY (
NATURAL RANGE <>)
OF
STD_LOGIC_VECTOR(
7 DOWNTO 0);
SIGNAL SMG_Buff : SMG_Buff_Type (
5 DOWNTO 0) := (X
"ff",X
"ff",X
"ff",X
"ff",X
"ff",X
"ff");
CONSTANT SMG_Code : SMG_Buff_Type (
0 to 9) :=
(X
"c0", X
"f9", X
"a4", X
"b0", X
"99", X
"92", X
"82", X
"f8", X
"80", X
"90");
每个process中对变量的操作不能够重复，不然FPGA就不知道同一时刻到底它的值是多少。因此采用这句Timer0IntSt <= not Timer0IntSt;注意复位的设计；
作者 [Antony] 2016 年 09月 27日
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