工具：vivado2015.2 板子：ZedBoard
module stream(
input clk,
input reset,
output [7:0] led
);
reg [31:0]count;
reg [3:0] num;
reg [7:0]led;
parameter[31:0] delay=32'd100000000; //delay 1 sec
always@(posedge clk or posedge reset)
begin
//clear
if(reset)
begin
num<=0;
count<=0;
end
else if(count==delay)
begin
num<=num+1'b1;
count<=0 ;
end
else if(num==8)
begin
num<=0;
end
else
count<=count+1'b1;
end
always@(*)
begin
case(num)
0:led<=8'b00000001;
1:led<=8'b00000010;
2:led<=8'b00000100;
3:led<=8'b00001000;
4:led<=8'b0001_0000;
5:led<=8'b0010_0000;
6:led<=8'b0100_0000;
7:led<=8'b1000_0000;
default led<=8'b0000_0000;
endcase
end
endmodule
管脚约束文件：
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports reset] ;
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports led[7]] ;
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports led[6]] ；
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS25} [get_ports led[5]] ;
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25} [get_ports led[4]] ;
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS25} [get_ports led[3]] ;
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25} [get_ports led[2]] ;
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS25} [get_ports led[1]] ;
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25} [get_ports led[0]] ;
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports clk] ;
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