ducoment for pyvexVEXIR

go :  angr.io/api-doc/pyvex.html /*---------------------------------------------------------------*/ /*--- begin libvex_ir.h ---*/ /*---------------------------------------------------------------*/ /* This file is part of Valgrind, a dynamic binary instrumentation framework. Copyright (C) 2004-2013 OpenWorks LLP info@open-works.net This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be used to endorse or promote products derived from this software without prior written permission. */ #ifndef __LIBVEX_IR_H #define __LIBVEX_IR_H #include "libvex_basictypes.h" /*---------------------------------------------------------------*/ /*--- High-level IR description ---*/ /*---------------------------------------------------------------*/ /* Vex IR is an architecture-neutral intermediate representation. Unlike some IRs in systems similar to Vex, it is not like assembly language (ie. a list of instructions). Rather, it is more like the IR that might be used in a compiler. Code blocks ~~~~~~~~~~~ The code is broken into small code blocks ("superblocks", type: 'IRSB'). Each code block typically represents from 1 to perhaps 50 instructions. IRSBs are single-entry, multiple-exit code blocks. Each IRSB contains three things: - a type environment, which indicates the type of each temporary value present in the IRSB - a list of statements, which represent code - a jump that exits from the end the IRSB Because the blocks are multiple-exit, there can be additional conditional exit statements that cause control to leave the IRSB before the final exit. Also because of this, IRSBs can cover multiple non-consecutive sequences of code (up to 3). These are recorded in the type VexGuestExtents (see libvex.h). Statements and expressions ~~~~~~~~~~~~~~~~~~~~~~~~~~ Statements (type 'IRStmt') represent operations with side-effects, eg. guest register writes, stores, and assignments to temporaries. Expressions (type 'IRExpr') represent operations without side-effects, eg. arithmetic operations, loads, constants. Expressions can contain sub-expressions, forming expression trees, eg. (3 + (4 * load(addr1)). Storage of guest state ~~~~~~~~~~~~~~~~~~~~~~ The "guest state" contains the guest registers of the guest machine (ie. the machine that we are simulating). It is stored by default in a block of memory supplied by the user of the VEX library, generally referred to as the guest state (area). To operate on these registers, one must first read ("Get") them from the guest state into a temporary value. Afterwards, one can write ("Put") them back into the guest state. Get and Put are characterised by a byte offset into the guest state, a small integer which effectively gives the identity of the referenced guest register, and a type, which indicates the size of the value to be transferred. The basic "Get" and "Put" operations are sufficient to model normal fixed registers on the guest. Selected areas of the guest state can be treated as a circular array of registers (type: 'IRRegArray'), which can be indexed at run-time. This is done with the "GetI" and "PutI" primitives. This is necessary to describe rotating register files, for example the x87 FPU stack, SPARC register windows, and the Itanium register files. Examples, and flattened vs. unflattened code ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ For example, consider this x86 instruction: addl