Introduction The QUP provides a general purpose data path engine support multiple mini cores. Each minicore implements protocol-specific logic. The common FIFOs provide a consistent system IO and system DMA model across widely varying external interface types. For example, one pair of FIFO can support SPI and I2C MiniCores independently. Currently supported MiniCores SPI I2C I2C Core: Support I2C Standard (100 kHz), and Fast (400 kHz) Key features added for MSM8909: BAM integration Support TAG (version 2) QUP base address for QUPs: In order to match the labeling of software interface manual, each QUP will be identified by BLSP core and QUP core (0 - 5). In hardware design documents, BLSPs are identified as BLSP[1:6] BLSP hardware ID QUP core physical address (QUP_BASE_ADDRESS): BLSP BLSP 1 QUP 0 0x78B5000 BLSP BLSP 1 QUP 1 0x78B6000 BLSP BLSP 1 QUP 2 0x78B7000 BLSP BLSP 1 QUP 3 0x78B8000 BLSP BLSP 1 QUP 4 0x78B9000 BLSP BLSP 1 QUP 5 0x78BA000 IRQs for QUPs: BLSP BLSP 1 QUP 0 95 BLSP BLSP 1 QUP 1 96 BLSP BLSP 1 QUP 2 97 BLSP BLSP 1 QUP 3 98 BLSP BLSP 1 QUP 4 99 BLSP BLSP 1 QUP 5 100 Configure QUP core as I2C in kernel This section describes steps necessary to configure any of the six QUP cores available in MSM8909 to configure and use as a I2C device. By default QTI already preconfigures BLSP1_QUP5 as I2C. See kernel/arch/arm/boot/dts/qcom/sim8909_evb103-msm8909.dtsi for more details. Following example shows how to configure BLSP1_QUP0 as I2C. 1. Create device tree node: User can use kernel/arch/arm/boot/sim8909_evb103-msm8909.dtsi
i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b5000 0x1000>; interrupt-names = "qup_irq"; interrupts = <0 95 0>; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; clock-names = "iface_clk", "core_clk"; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_1_active>; pinctrl-1 = <&i2c_1_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; dmas = <&dma_blsp1 4 64 0x20000020 0x20>, <&dma_blsp1 5 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; }; For latest detail plese follow : kernel/Documentation/devicetree/bindings/i2c/i2c-qup.txt Set up clocks: kernel/drivers/clk/qcom/clock-gcc-8909.c static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .c = { .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", .parent = &blsp1_qup1_i2c_apps_clk_src.c, .ops = &clk_ops_branch, CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c), }, }; static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = { .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR, .set_rate = set_rate_hid, .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, .current_freq = &rcg_dummy_freq, .base = &virt_bases[GCC_BASE], .c = { .dbg_name = "blsp1_qup1_i2c_apps_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP1(LOWER, 50000000), CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c), }, }; 2. Setup GPIOs: kernel/arch/arm/boot/sim8909_evb103-msm8909-pinctrl.dtsi pmx_i2c_1 { /* CLK, DATA */ qcom,pins = <&gp 6>, <&gp 7>; qcom,num-grp-pins = <2>; qcom,pin-func = <3>; label = "pmx_i2c_1"; i2c_1_active: i2c_1_active { drive-strength = <2>; /* 2 MA */ bias-disable = <0>; /* No PULL */ }; i2c_1_sleep: i2c_1_sleep { drive-strength = <2>; /* 2 MA */ bias-pull-down; /* PULL DOWN */ }; };Quick verification: This section describes how to quickly verify I2C bus. Check if the bus is registered. If you have entered all the information correctly, then you should see I2C bus. registered under /dev/i2c-#. Where cell-index would match the bus #. adb shell --> Get adb shell cd /dev/ ls i2c* --> to List all the I2C buses For example: root@android:/dev # ls i2c* ls i2c* i2c-0
i2c-1
