展开Verilog BUS信号名的方法

    xiaoxiao2021-12-14  18

    假如我有一些信号需要展开,信号的格式如下所示:

    input.file

    Hello/My/name/is/AAAAA[9:0] Hello/My/name/is/BBBBB[0:7] Hello/My/name/is/CCCCC[3:3] Hello/My/name/is/DDDDD

    展开之后的格式如下所示:

    Hello/My/name/is/AAAAA[9] Hello/My/name/is/AAAAA[8] Hello/My/name/is/AAAAA[7] ~~~此处省略若干行~~~ Hello/My/name/is/CCCCC[1] Hello/My/name/is/CCCCC[0] Hello/My/name/is/CCCCC[3] Hello/My/name/is/DDDDD

    下面的python脚本(python2)可以实现这个功能:

    expand_bus_bits.py

    #!/usr/bin/python import re fh = open('./input.file') for line in fh.readlines(): # print line m = re.match(r'(.*)\[(\d+):(\d+)\]', line) if m: signal_name = m.group(1) index0 = int(m.group(2)) index1 = int(m.group(3)) # print signal_name # print index0 # print index1 # print signal_name + "[" + str(index0) + ":" + str(index1) + "]" if (index0 > index1): while (index0 >= index1): print signal_name + "[" + str(index0) + "]" index0 = index0 - 1 elif (index0 < index1): while (index0 <= index1): print signal_name + "[" + str(index1) + "]" index1 = index1 - 1 else: print signal_name + "[" + str(index0) + "]" else: print line

    执行的结果默认输出到屏幕上。

    下面是输出的结果:

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